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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Recruitment Services |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Planning and Executing project deliverables on time to meet exacting standards and requirements of customers. Top level design and architecting of product solutions. Providing technical leadership while leading a team of engineers. Ensuring international industry standards in the product design and development. Must be a Bachelors / Masters in Electronics / VLSI / Microelectronics. Must have 8 years total experience in front end ASIC design (using Verilog / VHDL) Experience in development of IPs relating to USB 2.0 (Host and device ) Experience in validation of IP using FPGA at board level Exposure to design and development of bus interfaces such as AHB , and PCI Exposure to verification languages (such as VERA , SPECMAN) and functional modeling is desirable Awareness of industry standards in IP design and working knowledge of Synthesis tools (such as Synopsys Design Compiler is desirable Knowledge of datacom protocols would be an added advantage Experience in leading a team of engineers is a must. ,
Keyskills :
ips pci ahb vlsi asic fpga vhdl vera design verilog datacom sb bus specman