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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Consumer Durables / Electronics |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
- Sound knowledge of RTL frond end design principles. - Excellent command over HDL Verilog/VHDL. - Sound knowledge of FPGA design principles. Working with Xilinx/Altera FPGA is preferable. - Must have done RTL synthesis, constraints design, timing closure, RTL designs having CDC. - Must have written test benches to verify the RTL design. ,
Keyskills :
rtldesignverilogfpgavhdldesignoundlessvhdlverilogtestdiv