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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Xilinx is looking for a motivated Senior Verification engineer to join the Dynamic IP solutions Verification team in Hyderabad, India and work on challenging projects. At Xilinx we promote Growth Mindset ; If you are willing to learn and innovate along, Xilinx is the place to be!Looking for out of the box thinker that enjoys challenging projectsAs part of this team, you will play a key role in the verification of next generation FPGA- based intellectual property (IP) blocks and implement state- of- the- art Verification environments for the synthesizable IP cores.The engineer will work closely with Validation & Design teams and be a part of the global team of expert Verification Engineers.You will have the opportunity be a part of the innovation of FPGA- based IP blocks in areas like Compute Acceleration, Storage Solutions, Wireless, Embedded Vision, Industrial IOT, Cloud Computing, Machine learning.Qualifications10+ years of Verification experience in IP/ Silicon/ Subsystem Verification.Hands- on Experience in development of test bench architecture, test cases, functional & code coverage, running regressions and debugging tests; Ability to contribute to verification tasks with minimal guidance is required.Job responsibilities will span across from building scalable and re- usable test bench architectures to validation aspects in the long run.Experience with any one HDL simulator is good but need to be savvy with simulation/ methodology/ emulation and verification tools.Excellent Verilog, VHDL, Basics of C programming, System Verilog is a must.Should be able to work on multiple projects simultaneously and be very good at debugging/ problem solving.UVM/ VMM/ OVM experience is a mustExperience and Knowledge of AXI4/ AxiLite/ AHB is needed.Knowledge of other protocols such as Ethernet/ PCIE/ NVMe/ RoCE is a plus. Memory technology DDR, NAND & Chip level verification is a plus.Required thorough Understanding of Logic/ Digital Design Concepts and structures like Fifos, memories. Understanding of RTL Design concepts, and Synthesis flows.Preferred Scripting experience (Tcl/ Shell/ Makefile, Perl, Python etc.)EducationBSEE/ MSEE in EE/ CE with minimum 10 + years of relevant verification experience and looking for a Senior EngineerTap to unmuteIf playback doesnt begin shortly, try restarting your device.More videos on YouTube An error occurred while retrieving sharing information. Please try again later.,
Keyskills :
autocadcad drawingmodeling mechanicalmultiple projects simultaneously rtl designtest cases