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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Hardware / Networking |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Senior DFT engineer for Design- for- Testability work on leading edge ethernetswitch chips.Required: knowledge of DFT, scan, ATPG, IEEE1149.1/ JTAG, BIST, Verilog, logicand circuit design.Desirable: knowledge of IP block insertion, memory test, fault simulation, failure analysis, script programming, VLSI test equipment, silicon life cycle.Specify, implement, and verify DFT features.DFT insertion and sign- off at design sub- block level.Comprehend DFT methodology, and advise on improvements.Ensure that high coverage manufacturing test patterns are generated.Work on silicon bringup and debug.Education: BSEE required, MSEE preferred.Experience: 5- 8 years.,
Keyskills :
atpg dft scan silicon continuousimprovementfacilitation testequipment failureanalysis ip vlsi jtag bist edge design verilog circuit analysis equipment simulation mem ytest