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Senior Engineer I, ASIC Design

5.00 to 0.00 Years   Hyderabad   10 Dec, 2020
Microchip Technology Inc
Job LocationHyderabad
EducationNot Mentioned
SalaryNot Disclosed
IndustryConsumer Durables / Electronics
Functional AreaOccupational Health / Safety
EmploymentTypeFull-time

Job Description

SummaryAs a member of Microchip s engineering community, your primary responsibility will be to the design, integration, and verification support of the Full Chip Architecture and Full Chip Control/Data busses for an advanced ASIC or FPGA. Microchip s designs are an SOC with various Hard and Soft IP blocks that support a large number of industry standard protocols. Duties & ResponsibilitiesGeneral Full Chip Integration and Support

  • Detailed module design and integration, performance analysis and detailed design specification creation a large component of this position is to work with all design teams to ensure seamless integration of all components on the device.
  • Detailed ownership of full chip documentation of the SOC or FPGA device and/or device family.
  • Participate in the Verilog implementation and integration of full chip capabilities including interface support, integration of full chip busses (control and data network-on-chip) and documentation support at the full chip level.
  • Support full chip post-layout timing closure and verification
  • Participate in the investigation & assessment of legacy and emerging integration techniques and on-chip / off-chip network-on-chip (NOC) bus structures for both control and high speed data paths. Overall support of the full chip register map at the chip level is required.
  • Improve Data & Command processing bandwidth, reduce latencies & increase reliability
  • Support porting the design into test chips and emulation platforms
  • Support pre-tapeout verification and post-tapeout validation/characterization of the system designed
  • Work closely with FPGA support software and Firmware engineers to resolve hardware issues and customer issues
Job RequirementsEducation Required
  • Bachelors/Master s in electrical engineering, Computer Engineering or Computer Science.
Experience Required
  • Minimum of 5 years of proven silicon design experience in system level integration of many different internally developed and purchased full custom and ASIC IP blocks into a full chip environment. This would also include the integration of control and high-speed data network-on-chip (NOC) busses.
Requirements
  • Experience is SOC IP development and Full Chip Integration
  • Strong technical leader that is also able to work in a team oriented environment
  • Strong Experience in Verilog design and design verification
  • Strong Experience in Static Timing Analysis and Verilog simulation tools
  • Ability to write detailed design specifications
  • Good analytical, oral and written communication skills.
  • Able to write clean, readable presentations.
  • Self-motivated, proactive team player.
  • Ability to work to schedule requirements.
Beneficial Experience
  • FPGA, ASIC System and Embedded Processor Design Experience
  • Lab Experience for System Level Validation and Support
,

Keyskills :
safetycommissioningsiteinspectiontroubleshootinghigh speed datastatic timing analysisdetail designmodule designtiming closuretiming analysis

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