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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Consumer Durables / Electronics |
| Functional Area | Finance / Accounts / Tax |
| EmploymentType | Full-time |
Write verification specifications, verification plans, and documentationDevelop test bench and automate regression plansBe responsible for simulations, verifications, and debugging of logic designs (schematics, RTL)Be responsible for developing testbenches , test cases and verification flow components for Soc based FPGADevelop tests with software/firmware flow used in SoC FPGA verificationDevelopment of Behavioral models using Verilog and SystemVerilogDevelop Coverage driven Verification flowsDevelop and complete block-level verification and contribute on test development for SoC FPGA fullchip level verificationBring a self-motivated and enthusiastic approach that will achieve any new requirements andovercome all challengesAble to work independently and handle complex Block and Subsystem Verification platformAble to debug the logic designs for design intent and Interface with cross-functional teams andcollaboration in all verification related activitiesQualifications: BSEE or MSEERequired Skills and Experience:Hands on project experience in RTL VerificationStrong knowledge on digital fundamentals and understanding of FPGA/ custom chip flowHands on knowledge on Verilog and SystemVerilogHands on knowledge in C/ C++ languageExperience in FPGA programming and related software usage with Firmware handling knowledge is a plusExposure to SVF and STAPL/JAM: Adaptive FPGA Programming is a plusGood Knowledge in logic design and analysisExperience with UNIX shell scripting or Perl scriptingExperience in Verilog, SystemVerilog, UVMExposure to SoC FPGA flow conceptsExposure to Gate Level Simulations and Firmware VerificationExposure to knowledge on System Verilog Assertions, Functional Coverage and ScoreboardExperience with leading edge simulator tools is recommendedGood analytical and problem solving skillsExcellent written and verbal communication in English.Willingness to travel on short notices occasionallyJob RequirementsQualifications: BSEE or MSEERequired Skills and Experience:Hands on project experience in RTL VerificationStrong knowledge on digital fundamentals and understanding of FPGA/ custom chip flowHands on knowledge on Verilog and SystemVerilogHands on knowledge in C/ C++ languageExperience in FPGA programming and related software usage with Firmware handling knowledge is a plusExposure to SVF and STAPL/JAM: Adaptive FPGA Programming is a plusGood Knowledge in logic design and analysisExperience with UNIX shell scripting or Perl scriptingExperience in Verilog, SystemVerilog, UVMExposure to SoC FPGA flow conceptsExposure to Gate Level Simulations and Firmware VerificationExposure to knowledge on System Verilog Assertions, Functional Coverage and ScoreboardExperience with leading edge simulator tools is recommendedGood analytical and problem solving skillsExcellent written and verbal communication in English.Willingness to travel on short notices occasionally,
Keyskills :
financesales ltdmis accountancyunix shell scripting test caseslogic design system veril