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Senior Staff Physical Design Engineer

4.00 to 6.00 Years   Hyderabad   22 Mar, 2021
Job LocationHyderabad
EducationNot Mentioned
SalaryNot Disclosed
IndustryConsumer Durables / Electronics
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

DescriptionAt Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible. Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the worlds first 5G networks, we empower the worlds builders and visionaries whose ideas solve every day problems and improve peoples lives. If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.Responsibilities

  • In this role you will be responsible for Physical design of ASIC blocks or systems which are embedded in Xilinx ACAP devices
  • You will work with design and architecture to define products and refine design capabilities
  • Able to work independently and with limited supervision
  • Technical leader for less experienced team members
Job Requirements
  • Knowledge of deep sub-micron designs and manufacturing (7nm/5nm)
  • Deep understanding of ASIC physical design flows including Synthesis, DFT, Place and Route, STA, Extraction, Formal Verification, Physical Verification and EMIR verification.
  • Hands on usage and recent experience with ASIC design tools such as ICC2/Innovus/PrimeTime/Redhawk
  • Hierarchical design, Floorplanning and Clock tree design capabilities
  • Scripting knowledge such as Perl/Tcl
Education RequirementsMasters/ Bachelors in EE/EC/CS Years of Experience15,

Keyskills :
floor planningdrcroutingverificationcontinuous improvement facilitationbig dataasic designphysical designformal verificationcommunity engagementphysical verificationdftstacarelessleapasic

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