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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Telecom / ISP |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
KEY RESPONSIBILITIES: Strong knowledge in IPSOC design methodologies. Strong experience in Synthesis, timing, full chip netlisting & front-end design tools& flows Sound knowledge of RTL design with Verilogsystem Verilog Low power design Mentoring juniors and enhancing their skill set Must have strong knowledge of AMBA AHBAXI protocol Working knowledge on code coverage, functional coverage, Lint, CDC etc IP development and coding using standard coding guide lines knowledge Excellent communication skills. Must be able to participate & lead in global meetings Keyskills :
frontenddesign highperformancecomputing frontend rtldesign softskills codecoverage softwaredesign electricalengineering ip soc rtl cdc set vlsi lint amba sound design timing rontenddesign