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SoC/Chip Design Lead/Manager

6.00 to 10.00 Years   Hyderabad   13 Apr, 2020
Redpine Signals Inc
Job LocationHyderabad
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

The position requires strong knowledge of complex SoC/chip architectures with multi-core, multi-threaded processor subsystems, interconnects, memory architecture and caches, multiple clocks and resets, high-speed interfaces, peripherals. The candidate should be able to contribute to and own multiple development stages like architecture, microarchitecture, verification of SoCs which include ARM Cortex and proprietary processor designs, AMBA AHB/AXI/APB interconnects buses, high-speed interfaces for off-chip memories and be able to deliver reusable and robust IP. The candidate should have knowledge of SoC design flows and signoff criteria including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure. Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling) is part of the minimum requirements. The candidate is expected to work closely with the Software/Firmware, Silicon Validation/Characterization and Product Management teams. The candidate is expected to lead a team of engineers and be responsible for project management including preparing project plans and ensuring proper communication of milestones and status during the project.

Minimum Qualifications:
    Experience of architecting, implementing and verifying complex SoC/chip architectures with multi-core, multi-threaded processor technology, AMBA AHB/AXI/APB bus matrices, multiple clocks and resets and memory and cache architecture. Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI, CAN Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure Knowledge of DFT including Scan, MBIST Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling) Knowledge of Verilog and System Verilog
Preferred Qualifications:
    Knowledge of wireless technologies like WLAN, Bluetooth, ZigBee, GPS Knowledge of System Verilog, UVM, C/C++ Leadership and mentoring skills Project and Schedules Management with proper communication of milestones and status at different stages of the project Exceptional problem-solving skills Good written and oral communication skills
Education Requirements:
    B.Tech/M.Tech in ECE, EEE or CSE
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Keyskills :
html ui ads animation branddevelopment fmradio projectplans systemverilog timingclosure problemsolving projectmanagement productmanagement oralcommunication formalverification communicationskills irel

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