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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Rs 36 - 48 Lakh/Yr |
| Industry | IT - Software |
| Functional Area | Embedded, VLSI,Embedded / System Software |
| EmploymentType | Full-time |
SOC Full chip Timing Lead (FCT)Exp: 12-16yrsLocation: HyderabadJob DescriptionResponsible for schedule & quality goals. Drive & define FCT signoff criteria, setup, flow/methodology, constraints definition & validation, ACIO spec definition & validation & Syn & SD Caliber. Drive TR to achieve best convergence methodology/flow, globals ( VISA/STF/TAP/DTF ) network definition & IP specific custom checks. Expertise in all FCT Activities (Constraints definition & validation, TFM, efficient ECO methods etc ). Additional skills include- Hands-On experience with domain relevant industry standard tools like ICC, ICCII, Primetime, Redhawk, ICV, Calibre, Conformal, Spyglass-LP, Power Artist Etc. - Good understanding and exposure of overall SoC Cycle. - Good scripting skills in TCL/Perl/Shell to automate tool/flow methodologies. - You must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. - You shall be self-motivated with the initiative to seek constant improvements and driving new methodologies in the domain expertise.Qualifications & experience You must possess a Bachelor of Engineering degree or Master of Engineering in Electrical and/or Electronics Engineering with 12+ Years of relevant experience with the skills in Timing Closure .
Keyskills :
routevalidationelectronicsicctiming closurescriptingclock tree synthesisengineeringtimingclosureelectronics engineeringecoschedulesocprimetimetfmredhawkicciiplace