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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | Embedded, VLSI,Embedded / System Software |
| EmploymentType | Full-time |
SOC Physical Design Lead (Timing Closure)Exp: 15-20 yrsLocation: HyderabadSoC Physical Design Lead:Lead PD execution of partitions/subsystems/SoC with full ownership from synthesis to TI. Must have experience on 10nm and below technology nodes. Responsible for schedule & quality goals. Responsible for stake holder management inside & outside D2S organization.Drive TR to achieve best floorplan, package, PPA, TFM choice, signoff criteria & technology. Expertise in all Physical Design Activities (FP, APR, FCT, Clocking, PDN & LV).Additional skills include: - Hands-On experience with domain relevant industry standard tools like ICC, ICCII, Primetime, Redhawk, ICV, Calibre, Conformal, Spyglass-LP, Power Artist Etc. - Good understanding and exposure of overall SoC Cycle. - Good scripting skills in TCL/Perl/Shell to automate tool/flow methodologies. - You must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. - You shall be self-motivated with the initiative to seek constant improvements and driving new methodologies in the domain expertise.Qualifications:Qualifications & experience You must possess a Bachelor of Engineering degree or Master of Engineering in Electrical and/or Electronics Engineering with 15+ Years of relevant experience with the skills in Timing Closure
Keyskills :
physical designppaicvredhawkprimetimecalibresignoff criteriaspyglass-lpconformaltfm choicepower artisticc icciifloorplan package