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Job Location | Hyderabad |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | IT - Software |
Functional Area | General / Other Software |
EmploymentType | Full-time |
BS / MS with 5+ years of experience.
Expertise in the following languages: Perl, Tcl and Verilog
Expertise in the use of make
Experience in engineering flow development.
Exposure to FPGA compile tools, Xilinx tools a must.
Good SW debug and problem solving skills.
Knowledge of FPGA details a definite plus
,Keyskills :
problem solvingperlfpgaverilogdebuggingengineeringProblem AnalysisOperation MonitoringPlanningProblem SensitivitySocial PerceptivenessTeam Problem SolvingNumeracyDocumentationPrimetimeClock Tree SynthesisTiming ClosuretclxilinxDecisionM