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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Hardware / Networking |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Synthesis | Eximius Expertise in Synopsys Design Compiler Synthesis DCT/ DCG and/ or Cadence RC/ Genus Hands on in multi- voltage, power aware synthesis, UPF flows in synthesis Expertise in formal verification with Cadence LEC/ Synopsys VC formal Expertise in writing and debugging timing constraints Expertise in full chip STA, hands on in Primetime is a strong plus Good understanding of RTL to GDS flow. Expertise in Perl and/ or TCL scripting is a must Knowledge in Verilog and VHDL is a must AddThis Utility Fram,
Keyskills :
designcompiler vc tcl gds rtl sta upf perl vhdl design timing writing verilog cadence voltage scripting synthesis debugging primetime malverification