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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | TestingGeneral / Other Software |
| EmploymentType | Full-time |
At least 2 year experience in OVM/ UVM methalodologies.Experience with any of the bus protocols like AHB, AXI, OCP etc.Should have hands on experience in Functional coverage implementation and analysis.Should have exposure to atleast one IP level verification project.Basics of perl scriptingSet B :Very Good UVM Expertize with 4 Yrs Full chip SoC Verification Experience.Hands on Experience in UVM Verification Methodology.Good working knowledge of various Storage/ Wireless/ Networking domain protocols is added advantage.Involved in at least 3 SoCs in system level as well block level verification.Should have hands on GLS experience.Strong in usage of Assertions.Very Strong in System Verilog and able to build verification environment from the scratch.Any methodology transition is added plus.Engineers required work with our partners and also in our internal product development activities. ,
Keyskills :
systemverilog socverification productdevelopment ip soc uvm bus gls ocp axi ahb perl verilog protocols engineers implementation Plastics Adhesives InjectionMolding etw king