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| Job Location | Hyderabad |
| Education | Not Mentioned |
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| Industry | Recruitment Services |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Develop verification testbench components for chip/ module level using System Verilog, C & PerlUse high level language concepts (Object oriented, UVM/ OVM/ VMM etc) to develop extendable environment.Define and execute detailed verification plan from spec working with architects, designers, system engineers.Write tests, automate regression scripts and regression environment.Incorporate code- coverage, functional coverage, assertions, cover- groups etc to achieve 100% verification completeness prior to tapeout.Debug tests, run gate level simulations at unit/ sdf delaysDevelop automated/ scripted design flows for the above mentioned development processesParticipate in FPGA/ silicon debug and analysisExcellent debugging skills in both SW and ASIC hardwareMust be proficient in Verilog (System Verilog preferred) .Proficiency in scripting language like Perl, Tcl/ Tk, Shell is a definite plus.Experience with simulators like ncVerilog (Incisive) , VCS and QuestaSim.Good understanding of latest formal verification techniques, assertions, OOP etc is a plus.Understanding or prior experience with Industry standard protocols like USB, SPI, SATA, Ethernet, DisplayPort, SRIO etc is a definite plusBE/ B.Tech, MS 2- 10 years of experience.,
Keyskills :
verification uvm design failureanalysis ip systemverilog guidevelopment spi usb oop vcs vmm perl asic sata tests verilog silicon malverification