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| Job Location | Hyderabad |
| Education | Not Mentioned |
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| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
10+ years Experience Should have SoC and IP level Functional Verification experience of 6-10 Yrs. nExpert in System Verilog based Test Bench Architecture development nGood hands-on on SV-UVM based Test environment components implementation such as SV Testbench, drivers, monitors, scoreboards, checkers nShould have good ASIC/SOC System Level Architecture knowledge nDFX validation nFamiliar with System Verilog Assertions, Code and Functional Coverage and Formal verification techniques. nStrong working knowledge of any of these protocols: DDR, USB, PCIe, Ethernet, SATA,AXI. nExperience in setup and debug of gate level simulation nKnowledge of low power verification nKnowledge of synopsys tools is desired nStrong understanding of verification process from test plan to coverage completion nStrong communication and Analytical skills nProficient in debugging and issue fixing nGood Customer Orientation n, Roles & Responsibilities:Mandatory Skills: VLSI HVL Verification, System Verilog - SV Analog Circuit design, Hardware Designing, Analog and Mixed signal Verification Language Skills: English Language
Keyskills :
systemverilogcircuitdesignnalogcircuitdesigngatelevelsimulationmixedsignalsynopsystoolsanalyticalskillsmalverificationfunctionalverificationarchitecturedevelopment