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| Job Location | Noida |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Hardware / Networking |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
ASIC_Phy_Design_Engg Masamb Electronics Systems Vision : To be the number 1 choice of VLSI design and EDA houses for VLSI Design , Verification and Scripting. ASIC Physical Design Engineer Implementation of multi - million gate SoC designs from RTL to GDSII in cutting edge process technologies (130nm , 90nm , 65nm 45nm ) Will be working on all aspects of physical design including synthesis , floorplanning , bondout , place and route , clock distribution , IP integration , extraction , timing closure , power and signal integrity analysis , formal verification , DFM , and tapeout. Meeting challenging schedule , performance , and quality constraints.BE / BTech / MTech / MS in Electronics / Electrical / EC / EEE / EI 3 to 7 years of experience in block and chip level physical design (RTL to GDSII) Must have hands on experience on Synopsys and / or Cadence flow Experience on timing closure , clock / power distribution and analysis , P R , LVS , DRC and simulation. Knowledge of deep submicron processes Experience with power gating Experience with coding in Primetime , Formality , Perl , and TCL preferred Knowledge and experience in Verilog and VHDL preferred Proactive and self - motivated. Good communication skills Masamb Electronics Systems is a member of Chairman of the Board CEO and Managing Directo,
Keyskills :
planning drc routing verification ip vlsidesign timingclosure physicaldesign signalintegrity powerdistribution clockdistribution communicationskills tcl eda soc rtl dfm lvs lo malverification