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| Job Location | Noida |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Manufacturing |
| Functional Area | Operations Management / Process Analysis |
| EmploymentType | Full-time |
The Incumbent will be responsible for Synthesis, Constraint development and Timing SignOff of products related to Engine control , Safety(including airbag) , Body, Chassis and Advanced Driver Assistance System(ADAS) for futuristic cars.Responsibilities include guiding and reviewing work done by younger engineers along with being a strong technical contributor. This would involve strong communication and interpersonal skills , synthesizing and reporting data to management and customer.The job involve interactions with RTL/DFT designers to understand system and develop constraints for Synthesis and Implementation. Candidate will be responsible for Synthesis and Timing signoff for complete SOC while working with Implementation engineer at every stage for getting best QOR through optimum placement , CTS and timing closure for products involving state of the Art technologies like 7nm FINFET and 28FDSOI with high frequency and low power challenges. These SOC involve Integration of analog IPs and are Multi-supply, Multi-mode, Multi-corner having complex multiple clock structures. Constantly challenged to meet the automotive standards along with closing the design requirements., Expert in developing chip constraints working with RTL and DFT teamsStrong in Reporting to management and customerSynthesis and STA Expertise with synopsys/Cadence toolsCapable of working independently as well as technical leadKnowledge of full RTL to GDSII flow to take timing closure from RTL to signoffStrong communication and interpersonal skillsShould have good understanding of verilog/VHDLExposure to low power techniquesKnowledge of tcl and perl scripting is a mustShould have a strong sense of urgency.
Keyskills :
timingclosure interpersonalskills perlscripting art dft soc rtl sta perl design timing closure control chassis reporting placement scripting synthesis cl ips