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Lead DFT Design Engineer M/F

6.00 to 10.00 Years   Noida   09 Jun, 2022
STMicroelectronics
Job LocationNoida
EducationNot Mentioned
SalaryNot Disclosed
IndustryManufacturing
Functional AreaGeneral / Other SoftwareEngineering Design / Construction
EmploymentTypeFull-time

Job Description

    A DFT expert role as a task leader. The incumbent will be responsible for leading some of the activities of advanced DFT/DFD/DFM (design for test/debug/manufacturability) techniques for developing innovative products for automotive. The selected candidate will also be involved in all aspects of DFT including methodology development, design, pattern development, manufacturing tests and debug.The incumbent should be self-driven, adaptable, flexible, creative and capable of working independently. He/she needs to be a solution orientated individual with a quality driven and customer focused mindset.Responsibilities include but not limited to:DFT architecture specificationDFT RTL coding and integrationSCAN and Logic-BIST insertionHigh Speed interface DFT managementMemory BIST specification and insertionInteraction with Front End, Back End &Test Engineers located at various sites , Technical background/Key SkillsQualification: Bachelors/Masters in ElectronicsStrong DFT Fundamentals, Strong DFT Fundamentals, so as to be a Technical Mentor to the juniors End-to-end DFT execution for at least one complex SoCs, including silicon bring-up.Good RTL (VHDL or Verilog) writing skillsSOC integration and RTL modification as per DFT requirementGood at DFT DRC/Linting/Spyglass checksHands on experience with JTAG protocols, Scan and MBIST architectures and tools (SMS, MMB).Working Knowledge in scripting language (TCL, Perl, MASIS etc) and latest technique viz. Lowpower ATPG, Analog Bist, Logic Bist will be preferredWorking Knowledge of High-Speed interface testing is a plus (i.e. LPDDR4, PCI, MIPI)Expertise to use industry standard tools like Tetramax, Design Compiler, etc.Expertise in RTL, Gate-level simulations and debug, including silicon-debugWorking Knowledge of Boundary Scan Testing and testing of IPs viz ADC, FLASH , PMU in standalone mode.Expert leader in ATPG coverage analysis to achieve high test coverage at SoC level. PT2TMAX flow for ATPG STA is desirableExperience in follow-up/closure of tool issues with EDA CAD vendorsStrong teamwork and communication and quick learning are key skills

Keyskills :
drawingautocaddraftingmodelingcadcontinuous improvement facilitationfront endrtl codinglogic bistboundary scantest coveragecustomer focusdesign compilerinterface testing

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