Methodology Engineer

2.00 to 5.00 Years Noida 31 Aug, 2019

Job Location	Noida
Education	Not Mentioned
Salary	Not Disclosed
Industry	Manufacturing
Functional Area	Maintenance
EmploymentType	Full-time

Job Description

Bachelor or Master or Ph.D. in Electronics Engineering and specialization in VLSI domain.
Hands on experience in SoC level floor plan, power plan, IO ring, STA, Power integrity analysis and physical verification and defining analog / digital interface requirements
Proven experience in delivering full chip Static Timing Analysis (STA) closure methodology of mixed signal SoC with high speed PHYs, IOs, PMU IP etc. closing analog / digital interfaces timing & signal integrity issues
Experience in Synopsys Prime Time tool flow, Cadence Tempus tools, low geometry node issues, working with EDA team in reviewing & resolving blocking issues in project
Experience in customizing flows & methodology to meet low power & area objectives of SoC and leading team to execute on time
Ability to use scripting languages / automation of STA analysis methodology creation and deployment
Should have proven experience in demonstrating strong technical leadership to deliver on commitment, anticipation of challenges, assertive communication and excellent team player.
Excellent communication skills with proven experience in international relationships

Keyskills :
ul ios eda soc sta vlsi prime cadence security mu nxp timing closure embedded

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Methodology Engineer

Job Description

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