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Job Location | Noida |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | IT - Software |
Functional Area | General / Other Software |
EmploymentType | Full-time |
Design verification at RTL level is critical for time to market and various innovative ways are needed for faster verification. Emulation based verification had been grown significantly over years due to increase in design size and various verification complexity in all domain being functional validation, power verification/ estimation and most important performance. Extended verification complexity is needed to do shift left in verification area. Performance plays a significant role in emulation based validation to make sure design verification is done in time.Mentor emulation platform Veloce leads solving above challenges in all domains.The person in this role will be responsible for developing, enhancing and maintaining key technology components of the RTL Compiler (frontend RTL Synthesis for Veloce) of Mentor Graphics in verification domain. The candidate should have experience in EDA software, preferably in the RTL synthesis domain.
Keyskills :
rtlcompiler datastructures softwareprojects designverification softwaredevelopment technicaldiscussions optimizationstrategies eda rtl specs design software graphics synthesis emulation components entorgraphics