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Senior Lead STA Engineer

4.00 to 7.00 Years   Noida   13 May, 2022
NXP Semiconductors
Job LocationNoida
EducationNot Mentioned
SalaryNot Disclosed
IndustryManufacturing
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

    • Ability to understand advanced digital design architectures and clocking structures to help manage Functional/Scan/MBIST timing constraints with multiple clocks.
    • Expertise in SOC IO constraints developments.
    • May have to own bottom-up partition-level integration and top-down design partitions constraints.
    • Expertise in Advance Timing Analysis, Debug and timing convergence, ECO creation with signal integrity & EM/IR.
    • Knowledge about SDF, GLS, and able to debug timing failures.
    • Hands-on experience of working on technology nodes like 28nm, 16nm, 10nm, 7nm.
    • Good knowledge of EDA tools from RC, DC, PT, PTSI.
    • Good knowledge of Synthesis, Floor planning, place & route, power and clock distribution, pin placement and timing analysis.
    • Contribution in flow/methodology related scripting as part of design implementation.
    ,

Keyskills :
team managementcustomer relationsdeliverydocumentation

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