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Design Engineer II

2.00 to 7.00 Years   Pune   08 Nov, 2021
Cadence Design
Job LocationPune
EducationNot Mentioned
SalaryRs 2.0 - 7 Lakh/Yr
IndustryIT - Software
Functional AreaEngineering Design / Construction,General / Other Software
EmploymentTypeFull-time

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  • This position requires the development of reference C and optimized firmware for Baseband Signal Processing on Tensilicas configurable embedded processors.
  • Developing and Optimizing performance of signal processing firmware using C level changes, using C intrinsics.
  • Updating the firmware for features, interfaces and new processor configurations.
  • Understanding and analysis communication algorithms and standard
Required Skills
  • The candidate should have a good understanding of C and assembly language for a DSP or DSP-like processor.
  • Good understanding of basic DSP algorithms, fixed point arithmetic.
  • Knowledge of baseband signal processing is desired.
  • Exposure to VLIW, SIMD DSP processor architecture is desired
  • Good communication skill oral and written
We re doing work that matters. Help us solve what others can t.,

Keyskills :
rtl designdrawingautocaddraftingmodelingassembly languagesignal processingoptimizing performancedspsimdbasicertmsembeddedanalysisfirmwarebasebandfeaturesalgorithmscadence

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