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| Job Location | Pune |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Consumer Durables / Electronics |
| Functional Area | Service / Installation / Repair |
| EmploymentType | Full-time |
The roles and responsibilities of engineer require in-depth knowledge and hands-on experience across the entire spectrum of RTL2GDSII Implementation i.e. Synthesis, Floorplanning, Power Grid Design, Placement, Clock implementation, Routing, STA, Electrical signoff, Power-Analysis, Physical Verification, Chip finishing, etc.Interact with FE/BE design teams to prepare good floorplan and suggest appropriate changes to achieve PPA goalInteract with the design team to understand timing, CTS goals in detail to solve problems and propose physical design ideasDebug design, timing constraint issues and feedback to design teamAnalyze results from signoff checks and achieve design closureRequired Skills5 to 14 years of experience in Physical Design implementation and physical verification roleMust have led and been primarily responsible for at least 2 end-to-end multi-million gate-count hierarchical full-chip Physical design projectsAbility to plan and work independently and coordinate with cross-functional teamsMust have led and been primarily responsible for at least 2 end-to-end multi-million gate-count hierarchical full-chip Physical design projectsAbility to plan and work independently and coordinate with cross-functional teamsGood knowledge of low power concepts and application to PDLow power synthesis on blocks and subsystems using DC/Genus, Physical Aware synthesisExperience in design planning and Integration activityIO, Bump planning and RDL routing StrategyExperience in formal verification for RTL 2 gates and gates2gates, low power verification is a mustExposure to low-power designs with CPF/UPF flowKnowledge of CTS, Clock tree methodology and clock skewingPower grid, clock tree, and low-power reduction implementation methodsGood understanding of timing constraints developmentexcellent STA tool and timing concept understanding for analysis & debug of problems and closure methodologiesSignal integrity and timing closure issues such as OCV/AOCV/Statistical Timing/MMMC and multi-power designs (Level shifters, Isolation cells etc.)Must have experience in ECO implementationUnderstanding of Physical Verification Flows is an advantageProgramming and scripting skills (Tcl, Perl, etc.)Experience with cutting edge technology node designs like 16nm, 12nm, 7nmExperience of networking design would be a plusHands-on expertise with industry-standard EDA tools including but not limited to Design Compiler/RTL Compiler, Innovus/ICC2, Primetime/Tempus, QRC/StarXT, Calibre,
Keyskills :
linuxandroidautomationframeworkeda toolstiming closurecloud computingphysical designformal verificationspectrum managementintellectual propertyphysical verificationcorporate citizenshipedartlstaecoppa