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Job Location | Pune |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | IT - Software |
Functional Area | Engineering Design / Construction |
EmploymentType | Full-time |
As a member of the Logic Design Team for Xtensa processors you will be responsible for the development of microprocessor cores, single and multi-processor sub-systems and their peripherals. You will own creation of micro-architecture specifications for next generation features. You will design and implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other EDA scripts to meet timing, area and power goals. You will also assist with developing testplans, writing functional diagnostics, debugging failures and analyzing coverage information. You will work closely with the Design Verification and EDA teams. Required Skills and Experience: MS (or higher) in EE /Computer Engg. with 5 years of relevant design experience. Excellent logic design demonstrated by successful ASIC or SoC implementations. Knowledge of computer architecture and pipelined designs is essential. Experience in designing processors a plus. Excellent knowledge of Verilog and popular EDA simulation & implementation tools Good experience in scripting languages like Perl, Unix shell or similar languages. Experience with state-of-the-art verification methodologies (ex RTL assertions, coverage, etc) required. Excellent written and oral communication skills necessary. Good team player and interpersonal skills. We re doing work that matters. Help us solve what others can t.,
Keyskills :
nextasicadministrationmanagementunixlogiceducationcommunicationperledadiagnosticsenglishartnterpersonalskills