Design Verification Engineer

Job Description

Greeting form Globex Digital.!Please find the job description for _Design Verification Engineer interested please revert back with updated resume.JD: Design Verification EngineerExperience: 5-15 YearsLocation: Bangalore, HyderabadMode: Full TimeNP: Immediate-90daysJD DesignVerification:Understanding the business requirements and functional specifications of the IPs, subsystems and SOCCreating VerificationEnvironment Architecture documentReviewing and Revising: working towards meeting agreed upon acceptance criteriaDeveloping code in System Verilog, UVM (Universal VerificationMethodology), C for Unit, Subsystem and SOC level verificationPerforming RTL simulations using Synopsys and Cadence simulatorsDebugging and resolving problems found by simulations .Performance test plan development and maintenanceDevelopment of transactors, monitors and models for performance verification.Implement performance verificationflow including monitoring, synchronization, reporting and self-checking mechanismsProvide full report of performance metrics and bottlenecksTracking tickets and code releases using Bug Tracking tool and GITPerforming UPF (Unified Power Format) based Power Aware simulationsCoding of Assertion and Functional Coverage bins in SVA (System Verilog Assertions)Code & Functional Coverage ClosurePerforming Gate Level simulations .Preparing and conducting reviews of VerificationSign-off documents to ensure SOC tape-out qualityThanks & Regards,Rahul|Senior HR Executive (TA) Email: hidden_emailwww.globexdigitalcorp.com

Keyskills :
uvmsystem verilogdesign verificationsub systems