Analog / Mixed-Signal Circuit Design Enginee

Job Description

Key ResponsibilitiesCircuit Design & ArchitectureDevelop transistor-level circuit designs for analog/mixed-signal macros across advanced CMOS process nodes (28nm, 16nm FinFET, 7nm, and below)Architect and implement LDO regulators, bandgap references, and POR circuits with precision bias networks meeting tight temperature, supply, and process variation targetsDesign high-speed receiver (RX) front-ends, clock-data recovery (CDR) loops, DLL, and PLL circuits targeting multi-Gbps serial interface standardsImplement transmitter (TX) drivers with programmable swing, pre-emphasis, and equalization for PCIe, USB, MIPI, DDR, and custom SerDes linksDesign DC-DC switching converters, charge pumps, and analog switch circuits optimized for efficiency, area, and EMI complianceDevelop oscillator circuits (ring, relaxation, LC) and clocking distribution networks meeting phase noise, jitter, and duty-cycle specificationsDesign under-voltage and over-voltage protection circuits including supervisory functions, brown-out detection, and soft-start controlCreate bias generator networks, current references, and common-mode feedback circuits supporting system-level analog infrastructureSimulation & VerificationPerform comprehensive SPICE-level simulations (DC, AC, transient, noise, Monte Carlo, and corner analysis) using Cadence Spectre, HSPICE, or equivalentConduct behavioral modeling in Verilog-A / Verilog-AMS to enable system-level mixed-signal co-simulationExecute process, voltage, and temperature (PVT) corner verification to guarantee robust, first-time silicon successPerform post-layout simulation with extracted parasitics (RC/RLC) and validate performance degradation vs. schematic targetsCollaborate with physical design/layout engineers to review parasitic impact and guide layout techniques (shielding, symmetry, matching)Generate and maintain comprehensive simulation decks and regression test benches for IP re-use and future node portingSpecification, Documentation & ReviewAuthor detailed circuit design specifications, schematic documentation, and simulation result reportsParticipate in and lead design reviews, peer reviews, and architectural trade-off analysesInterface with system architects and SoC integration teams to define block-level requirements and pin specificationsSupport IP characterization, datasheet generation, and application note creationSilicon Validation & Bring-UpDevelop bench test plans and support silicon bring-up and characterization of first-pass prototypesAnalyze measured silicon data vs. simulation predictions, identify failure modes, and drive root-cause analysisPropose and implement design fixes and revision updates based on silicon findingsWork with test engineering teams to develop automated production test solutions (ATE) for manufactured siliconCollaboration & MentorshipWork in close partnership with layout engineers, DFT engineers, and SoC integration teams throughout the full design cycleMentor junior circuit designers and contribute to engineering capability building within the teamParticipate in foundry interactions, PDK evaluations, and device model reviewsRequired Qualifications Bachelor of Science in Electrical Engineering (BSEE) MandatoryMinimum 3 years of professional experience in analog/mixed-signal IC circuit designProficiency with Cadence Virtuoso Schematic Editor and Analog Design Environment (ADE-L/XL/GXL)Hands-on SPICE simulation experience using Spectre, HSPICE, or Eldo including Monte Carlo and PVT corner analysisDemonstrated design experience with at least 3 of the macro categories listed in the Circuit Design Scope sectionSolid understanding of MOSFET device physics, noise analysis, stability (phase margin), and mismatch/variation effectsFamiliarity with FinFET or advanced CMOS process node design constraints and device modelsKnowledge of analog design fundamentals: op-amp topologies, feedback theory, frequency compensation, and bandgap referencesPreferred QualificationsExperience with high-speed serial interface standards: PCIe Gen 4/5, USB 3.x/4, DDR5, MIPI, or custom SerDes at 10112 GbpsProficiency in Verilog-A / Verilog-AMS behavioral modeling for system-level mixed-signal simulationPrior collaboration with foundries such as TSMC, Samsung, GlobalFoundries, or Intel Foundry

Keyskills :
analog circuit designschematic