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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Manufacturing |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Responsible for Co- simulation of mix signal IPs of SERDES and Memory PHY. Designing behavioral models of mixed signal designs for use in functional verification. Developing a generic modeling framework in System Verilog that can be reused for various designs. Documenting the model functionality, architecture and usage model. QualificationsDesired Skills and Experience Electrical/ Electronic/ CS Engineering degree Expert in co- simulation methodology and toolset. Prior working experience of System- Verilog and UVM is must. Knowledge of DDR3/ 4, High Speed SERDES Protocols etc. Clear communication and presentation skills. Relevant Experience - 3 - 6 Years Good to have - Knowledge of C , System- C, Verilog- A languages, and modeling Virtual Platforms is appreciated. Hspice/ Spectre spice language understanding DSP concepts,
Keyskills :
systemverilog dsp ips uvm serdes hspice verilog spectre protocols simulation engineering architecture presentation communication ixedsignal commercialmodels kingexperience spice ertms