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ENGR SR PRIN, DIGITAL_TL

10.00 to 15.00 Years   Chennai, Hyderabad, Delhi   11 Jul, 2022
ON Semiconductor Technology India Private Limited
Job LocationChennai, Hyderabad, Delhi
EducationNot Mentioned
SalaryNot Disclosed
IndustryConsumer Durables / Electronics
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

    * Job Description DFT architect to define test architecture for WIFI MAC/Baseband SOC and implement the same. The candidate must have strong knowledge of Design for test for low power SOC. Ideal candidate must have experience of 10 to 14 years in DFT domain, working independently to provide complete DFT solution for SOC. Desired Skills and Qualifications
    • Experience in Scan insertion, MBIST, Boundary scan, JTAG, EDT insertion.
    • Block level Test pattern Generation (ATPG) and simulation
    • Post Silicon debug support experience
    • Simulator Tools experience: NCSim/Modelsim
    • Working experience in Tessent Test Solutions, Fastscan/ Testkompress /DFTAdvisor/Spyglass
    • Scripting Skills:Perl/TCL
    • DFT architecture definition w.r.t. test time/cost, coverage, test power.
    • Good experience/concept on all aspect of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan.
    • Good experience in memory repair implementation
    • DFT logic integration and verification.
    • Experience on debugging low coverage.
    • Gate Level DFT verification with and without timing.
    • Experience of leading small DFT team is plus.
    • Good experience on EDA tools of reputed vendor like Mentor, Synopsis.
    • LBIST experience is plus.
    • DFT mode STA and timing closure support.
    • Familiar to Verilog and RTL simulation.
    • Strong knowledge and experience in Scan Insertion, TestKompression, ATPG, Memory BIST and JTAG at IC
    • Should have been involved in minimum 4 tape out working independently, providing the test solution.
    • Need to have good understanding on the low power technologies like Power Island in SOC and tuning the DFT structure according to it.
    • Excellent communication skills both written and verbal.
    • Excellent collaboration skills.
    Responsibilities
    • Come up with DFT Architecture both at block and Full chip level.
    • Work independently on inserting the Scan, Test compress, JTAG, Mbist, and boundary scan structure in the Chip.
    • Generate the ATPG pattern and simulate the pattern on RTL/Netlist with/without timing.
    • Implement the MBIST repair solution for SOC
    • Work on generating the DFT SDC to be used by PnR flow.
    • Work on post silicon debug of ATPG pattern and chip bring up.
    , *
    • Bachelors with 10+ years of experience

Keyskills :
eda toolsboundary scantiming closurescan insertioncommunication skillsdft verificationedadftsocrtlstapnrwifiatpgjtagbisttapescanideal

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