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Job Location | Gurugram |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | IT - Hardware / Networking |
Functional Area | General / Other Software |
EmploymentType | Full-time |
Must be familiar with industry standard tools and methodologies.Must know Verilog.Verification candidates must know one of the following : SystemVerilog, Vera, SystemCWorking knowledge of synthesis, static timing analysis would be beneficial.Prior experience of working on arithmatic datapaths would be helpful for design candidates.Experience with the entire frontend design cycle would be desirable. It would be even better, if candidate has worked closely with backend team, specially for timing closure.Must be a team player, confident and self motivated.,
Keyskills :
verification uvm design failureanalysis ip statictiminganalysis frontend asicdesign timinganalysis it vera timing backend verilog closure analysis synthesis TimingClosure Primetime sic