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Lead Engineer FPGA Design

8.00 to 10.00 Years   Gurugram   10 Dec, 2019
Ciena India
Job LocationGurugram
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Hardware / Networking
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

Responsibilities:Develop complex FPGA logic architecture, code, simulation, and Verification.

  • Hands on bench testing of new designs for compliance to design specifications.
  • Complete documentation throughout design and development cycle from theory of operation to test specifications
  • Responsible for communication and coordination with Software, Hardware, System Engineering and Validation, teams throughout the design and development cycle
  • Coordinate with technical team members design reviews, feature specifications, etc.
  • Attend meetings, report progress, and take technical leadership to troubleshoot and fix defects.
  • Provide guidance and mentoring for junior engineers hired into the team who may be tasked to perform some of the above duties.
  • Help investigate and collect information to resolve process or design issues found on a current design or in previous designs.
  • Assumes other duties as assigned
General Activities:
  • High speed FPGA/IP block logic design for Packet Networking equipment.
  • Design of Layer 2 or Layer 3 IP blocks for Ethernet/IP protocols with packet parsing, switching, routing, traffic management, scheduling, shaping, admission control functions in FPGAs or ASICs with 1Gb Ethernet to 400Gb Ethernet/IP designs.
  • Knowledge with industry standards such as IEEE 802.3 standards for 1/10G , 100G Ethernet PCS and MAC layers , OAM , SAT , MEF standards, ITU-T standards, relevant RFCs such as Pseudowires, Ethernet metering etc. 5G Radio fronthaul standards such as RoE(Radio over Ethernet), Open RAN, CPRI/eCPRI standards.
  • FPGA/ASIC front end design using synthesis and simulations tools with System Verilog and/or VHDL.
  • Worked as design lead for full FPGA/ASIC or IP blocks.
  • Timing closure for FPGA or ASICs. Fully aware for timing constraints and methodologies.
  • Keen to develop FPGAs/ASIC blocks with high quality following rigorous quality checklists and methodologies.
  • Experienced with PERL/Python scripting.
  • Block/IP level verification of the same.
  • Validation of such FPGA/ASIC in System towards final deliverables.
  • Strong knowledge of using design tools for analysis, development, testing, and debug.
  • Knowledge and experience designing with Altera/Intel and Xilinx FPGAs with Quartus or Vivado tools.
  • Use of standard bench level test equipment such as oscilloscopes, logic analyzers, and other supporting equipment.
  • Ability to resolve complex issues that may require design trade-offs.
  • Excellent verbal and written communication skills.
DESIRED CHARACTERISTICS
  • Self-starter with positive attitude
  • Team orientation, organized, and capable of independent work
  • Acumen for problem solving. Ability to lead in an environment of change flexibility, creativity and patience
  • Ability to learn and grasp technical concepts related to products being developed
  • Able to work effectively and communicate at all levels within the Ciena workforce
Experience:
  • B.E/BTech in Electronics Engineering and/or M.Tech preferred
  • Minimum 8 years experience doing FPGA/ASIC design from requirements, using FPGA development tools with Verilog and/or VHDL.
Rewarding experience. Meaningful outcomes.Making a difference in peoples lives through design and implementation of leading network technologies. Thats what motivates us.A distinct way to workFree thinking, free discussion, and collaboration are the norm. Expect more satisfying outcomes - both personal and professional.Ciena values the diversity of our workforce and respects its employees as individuals, regardless of race, nationality, religion, sexual orientation, gender or age.Ciena is also committed to developing inclusive, barrier-free selection processes and work environments. If contacted in relation to a job opportunity, you should advise Ciena in a timely fashion of the specific needs / accommodation measures which must be taken to enable you to be assessed in a fair and equitable manner. Information received relating to any specific needs / accommodation measures will be addressed confidentially.What you can expect from us
  • You will receive notification of your successful application
  • Successful applicants will be contacted by Talent Acquisition for an initial discussion
  • If suitable you will be considered for the short list and our formal interview process
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Keyskills :
linux automation java rontenddesign testequipment workeffectively systemverilog developmenttools customerrelations ieee8023 talentacquisition logicdesign

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