Senior ASIC RTL Engineer

Job Description

Job Title: Senior ASIC RTL EngineerExperience: 6 - 22 YearsLocation: Bangalore / Hyderabad / Kochi / PuneNotice Period: Immediate 60 DaysOpen Positions: 25Band: B2 / B3 / C1Employment Type: Full-timeJob DescriptionWe are looking for an experienced Senior ASIC RTL Engineer with strong expertise in IP/Subsystem RTL design targeted for SoC. The role involves RTL development, integration, quality checks, and close collaboration with verification, physical design, DFT, and software teams to deliver high-quality silicon.Key Responsibilities
• Design and develop RTL for IPs, subsystems, and SoC integration using Verilog/SystemVerilog
• Perform RTL quality checks including Lint and CDC analysis
• Work on static checks and support synthesis and low-power design activities
• Integrate and debug multiple subsystems at IP, cluster, and SoC level
• Support PD, Verification, DFT, and SW teams on design queries and reviews
• Create and review design documentation for multiple subsystems
• Debug complex design issues across multiple blocks and interfaces
Mandatory Skills
1. RTL Design, Coding & Integration (Verilog / SystemVerilog)
2. RTL Quality Checks Lint & CDC (Spyglass)
3. SoC / IP / Subsystem Design & Integration
4. AMBA Bus Protocols (AXI, AHB, APB, ATB)
5. Interface Protocols PCIe / DDR / Ethernet / I2C / UART / SPI
Additional Skills (Good to Have)
• Knowledge of synthesis and low-power techniques
• Strong understanding of timing concepts
• Experience with tools: Spyglass, Synopsys DC, Verdi, Xcellium
• Scripting knowledge: Make, Perl, Shell, Python
• Understanding of processor architecture and/or ARM debug architecture
If you have strong expertise in ASIC RTL and SoC/IP design and enjoy working on complex silicon subsystems and protocols, wed be happy to have you apply and be part of our growing engineering team.

Keyskills :
codingcdcethernetintegration