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ENGR PRIN, DIGITAL_TL

10.00 to 14.00 Years   Kolkata   14 Mar, 2022
ON Semiconductor Technology India Private Limited
Job LocationKolkata
EducationNot Mentioned
SalaryNot Disclosed
IndustryConsumer Durables / Electronics
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

    * Job Description Candidate needs to work in the team involved in WIFI chipset development. Ideal candidates must have strong back ground in ASIC front end flows which involves, ASIC synthesis using one of leading tools like Genus or DC, Logic Equivalence using LEC/FEV, and low power static checks using CLP/Questa in UPF/CPF flow. Candidate must work with RTL designers to create the SDC and physical design engineers to set up the physical aware synthesis. He must analyze the timing reports and come up with the right strategy in synthesis to close the timing, area and power targets in synthesis. Looking for bright ASIC design engineers with excellent analytical and technical skills Desired Skills and Qualifications
    • 10-14 years of Synthesis and ASIC design work experience
    • Extensive experience in Synthesis with RC/RCP/Genus or DCT/DCG an absolute must.
    • Complete knowledge of ASIC flow with low power, performance and area optimization techniques
    • Experience with STA using Primetime and PTPX required
    • Proficient in constraint generation is must
    • Experience of multiple power domain implementation with complex UPF/CPF definition required
    • Formal verification experience (Formality/Conformal) is needed
    • Perl/Tcl/Makefile based scripting experience is required
    • Low power implementation techniques experience
    • Strong problem solving and ASIC development/debugging skills and Verilog coding experience
    • Place and route tool experience is plus
    • Excellent communication skills both written and verbal.
    • Excellent collaboration skills.
    , * Responsibilities
    • Participate on a project involved in the development of ASICs, with emphasis in synthesis, timing closure, low power, place and route
    • Develop constraints, run physical synthesis, low Power checks, timing and power analysis.
    • Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward
    • Work closely with RTL design, physical design, low power and automation teams to optimize performance and power
    • Generate, review and validate design constraints to achieve timing closure of High-speed cores.

Keyskills :
timing closureproblem solvingasic designasic synthesisdesign of experimentscommunication skillstechnical skillsphysical designfront endphysical synthesis

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