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Job Location | Noida |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | Recruitment Services |
Functional Area | General / Other Software |
EmploymentType | Full-time |
Title DDR verification,System verilog,ASIC engineer,UVM, 5+ years, Noida, Immediate joiners Apply Now Categories Embedded Jobs Salary As per industry standards Total Yrs Of Experience Required 5-10 Job Location Noida Job Descriptiono Experienced ASIC Verification engineer responsible for implementing and executing verification plan to verify DDR memory Controller/PHY features.o Requires a strong background in digital verification from planning to coverage closure.o Previous experience designing configurable IP is a strong plus.o 5+ Years of experience in verification using SV/UVM at IP level.o Desired skillso Knowledge of DDR memory protocolo Knowledge of Python or Perl for scriptingo Experience with highly configurable designsCandidates who can join immediately or within 30 days are preferred.Apply Now,
Keyskills :
dacssensorsverificationsystem verilogasic verificationuvmddrperlpythonsalaryverilogembeddedplanningRTL DesignStatic Timing AnalysisTiming ClosurePhysical Designipsasic