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| Job Location | Noida |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Manufacturing |
| Functional Area | Embedded / System Software,General / Other Software |
| EmploymentType | Full-time |
The position is an exciting opportunity to be part of a flexible and dynamic team in the growing markets of mixed signal chips with signal processing IPs, ARM processor and AMBA bus interface like Wireless Chargers, Bluetooth, PMIC etc. used in Mobile, Tablets, Microcontrollers etc.The role works within the digital verification team in Greater Noida collaborating with the design and verification teams in Italy and Singapore creating SV UVM based verification environment, using various apps of JasperGold to ensure design quality and qualify the testbench using Certitude.Job scope:Technical management of assigned project and leading digital verification team for IP or SOC verification.Hands on working experience in IP verification or SOC verification.Verification planning using v-plan, functional points identification, and review.SV UVM based test-bench development.ARM or processor based SOC verification experienceImplementation using different verification techniques (constraint random dynamics simulation and static formal verification).Verification closure by ensuring 100% code and functional coverage.Schedule preparation and execution adhere to plan.Present reports to the management., Role Purpose: To lead SoC verification activities and can work as Individual contributor too.- Masters in Electronics Engineering (a relevant experience with minimum 10 years in a semiconductor or high technology R&D environment would be appreciated)- Strong fundamentals in digital design, microprocessor, C language, OOPs, logical analysis, debugging, root cause analysis.- Experience to Metric Driven Verification flow with implementation using UVM based methodology. System Verilog & Assertions, Formal verification, C/C++ IP/SoC verification centric- Experience of working with Architecture, design and software teams to drive the verification activities & ensure micro-architecture and design is fully verified- Experience of IP/Subsystem/ASIC verification following MDV flow.- Strong foundation in SoC architecture and verification of single core/multi-core processors preferably ARM/DSP/RISC based- Understanding and experience in verification of AMBA Interconnect, DMA controllers, Interrupt handling etc. in ARM based SoC environment- Understanding of compilers and tools for ARM or equivalent processors- Hands on experience in UPF/CPF based Power aware verification (Low power designs)- Hands on experience in Gate level simulations verification environment bring up and debug- Proficient knowledge of SV, Verilog, VHDL, C/C++, HVL based methodology (UVM) and hands on scripting experience for automation using SHELL/PERL/PYTHON- Understanding of coverage closure goals in SoC Verification- Familiarity with achieving 100% functional coverage, Code Coverage and test plan coverage goals- Hands on experience with Test bench development from scratch, test case coding and execution.- Strong analytical problem solving, and attention to details- Strong skills related to DV Documentation, DV reviews- Strong understanding to derive test plan from design specification.- Good communication and written skills in English.- Able to work in a multi-cultural team.- Strong analytical and problem-solving skill.-Able to keep up with fast moving new verification methodology.
Keyskills :
root causemixed signalarm processorcode coveragesystem verilogdigital designsoc verificationsignal processingformal verificationarmsocuvmbusips