| Hyderabad Jobs |
| Banglore Jobs |
| Chennai Jobs |
| Delhi Jobs |
| Ahmedabad Jobs |
| Mumbai Jobs |
| Pune Jobs |
| Vijayawada Jobs |
| Gurgaon Jobs |
| Noida Jobs |
| Hyderabad Jobs |
| Banglore Jobs |
| Chennai Jobs |
| Delhi Jobs |
| Ahmedabad Jobs |
| Mumbai Jobs |
| Pune Jobs |
| Vijayawada Jobs |
| Gurgaon Jobs |
| Noida Jobs |
| Oil & Gas Jobs |
| Banking Jobs |
| Construction Jobs |
| Top Management Jobs |
| IT - Software Jobs |
| Medical Healthcare Jobs |
| Purchase / Logistics Jobs |
| Sales |
| Ajax Jobs |
| Designing Jobs |
| ASP .NET Jobs |
| Java Jobs |
| MySQL Jobs |
| Sap hr Jobs |
| Software Testing Jobs |
| Html Jobs |
| Job Location | Noida |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.In this job, you will be responsible for development of Formal Verification IPs using Verilog design models and System Verilog Assertions for various industry standard bus protocols.This role offers front row access to the cutting edge innovation happening in Formal Verification and an opportunity to master a variety of protocols.Follow below links for more information on the Cadence JasperGold platform and Formal Verification IP Protocol portfolio-https://www.cadence.com/en_US/home/tools/system-design-and-verification/formal-and-static-verification/jasper-gold-verification-platform.htmlhttps://www.cadence.com/en_US/home/tools/system-design-and-verification/formal-and-static-verification/jasper-gold-verification-platform/assertion-based-verification-ip.htmlMinimum Qualifications:Bachelors Degree5 or more years industry experience or Master s Degree3 or more years of experience as a RTL Design and/or Verification Engineer.Position Requirements:- Very good understanding of HDLs (Verilog, System Verilog for design) and System Verilog Assertions is MUST- Knowledge of at least one industry standard protocol (for example AHB, AXI, CHI, PCIe etc) is a MUST- Strong verification concepts like understanding spec, creating test plans, adding coverage is required- Strong analytical and problem solving skills required- Formal verification knowledge will be a plus- Experience in process automation with Python/TCL scripting will be a plus- Experience in mentoring juniors or new hires will be a plus- He/she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/verification problems using these tools.- He/she should have good communication skills.We re doing work that matters. Help us solve what others can t.,
Keyskills :
jqueryjavamvcsql servercustomer relationseda toolsnew hiresrtl designsystem verilogproblem solvingprocess automationformal verificationedartlbusaxiahbpcieips