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SENIOR DESIGN ENGINEERING

3.00 to 5.00 Years   Noida   18 Oct, 2019
NXP Semiconductors
Job LocationNoida
EducationNot Mentioned
SalaryNot Disclosed
IndustryManufacturing
Functional AreaEngineering Design / Construction
EmploymentTypeFull-time

Job Description

NXP Semiconductors enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer. As the world leader in secure connectivity solutions for embedded applications, we are driving innovation in the secure connected vehicle, end-to-end security & privacy and smart connected solutions markets.Key Responsibilities:

  • Evaluate and deploy the evolving verification methodologies to handle increasingly complex SoC/IP designs within aggressive, market-driven schedules.
  • Ensure quality adherence during all stages of the project life cycle. Also carry out a thorough analysis of existing processes, recommend and implement process improvements to ensure Zero Defect chips
  • Building and Influencing technological innovations for self and in team environment.
  • Ability to work well as part of a team both locally, and also with remote or multi-site teams.
Key Skills:
  • Self starter with 3-5 years of experience on IP / Sub-system / Chip-level verification on multimillion Gate and complex Design with multiple clocks and power domains with minimal supervision
  • Testbench and Testplan development to ensure thorough verification, address Testability aspects, Analog/Mixed signal aspects of the IP / Chip along with functional requirements
  • Experience in microcontroller architecture, Cache, protocols like AHB/AMBA,AXI, Memory(Flash, SRAM,DDR) and memory controllers
  • Experience in automotive protocols like LIN, CAN, Flex, Graphics/Multimedia/Networking protocols like Ethernet, USB, ITU656 would be an advantage
  • Experience and working knowledge of HVLs (UVM/SV/C++/SC/e/VERA), HDLs (Verilog/VHDL),PLI/DPI, simulators (NCSim/VCS/ModelSim/Questa)
  • Good Exposure to formal verification methodology, assertions/SVA, functional coverage, gate level simulations, verification planner and regression management
  • Experience in Low power verification using CPF/UPF would be a big plus
  • Exposure to pre silicon validation/emulation is an added advantage
  • Exposure to tagging and traceability requirements for Safety and understanding of ASIL levels would be advantageous.
BE/ME (Electronics),

Keyskills :
quality adherenceconnectivity solutions designembedded analysisprotocols adherence

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