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Sr. Engineer IP Design

6.00 to 10.00 Years   Noida   09 Sep, 2019
NXP Semiconductors
Job LocationNoida
EducationNot Mentioned
SalaryNot Disclosed
IndustryManufacturing
Functional AreaEngineering Design / Construction
EmploymentTypeFull-time

Job Description

NXP Semiconductors enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer. As the world leader in secure connectivity solutions for embedded applications, we are driving innovation in the secure connected vehicle, end-to-end security & privacy and smart connected solutions markets.Key Responsibilities

  • Architect and Design complex IP and Subsystems across a range of protocols required for Automotive Self Driving Vehicles (ADAS) both Vision and Radar, In-Vehicle networks, Gateway Systems, Fail Safe Subsystems (ASIL-D) etc.
  • Own and Lead IP / Subsystem from Concept till IP Design and Development achieving final design performance in integrated system within aggressive, market driven schedules.
  • Ensure quality adherence during all stages of the IP development cycle and carry out a thorough analysis of existing processes, recommend and implement the process improvements to ensure Zero Defect designs.
  • Ability to work well as part of a team of global and local experts to influence and build technological innovations.
Key Skills
  • Self starter with 6-10 years of experience to Architect and Design complex IP design / Sub-system with minimal supervision.
  • Custom Processor Designs with key DSP functions like those needed for Vision and Radar processing.
  • Experience in High Speed Serial protocols and associated high speed challenges on controller and PHY for PCIe, Ethernet & MIPI CSI2.
  • Understanding of key External Memory interface protocols including DDR4 / LPDDR4, QuadSPI Flash interfaces.
  • Experience in microcontroller architecture, Cache, protocols like AHB/AMBA,AXI.
  • Experience in automotive protocols like LIN, CAN, Flexray would be advantageous.
  • Extensive hands on knowledge of HDLs (Verilog/VHDL), Scripting languages (Perl, Tcl), C/C++ for hardware modeling.
  • Understanding of end to end IP development flow including complex CDC, RDC constructs, IP Synthesis, DFT ATPG coverage.
  • Work on Testbench and Testplan development closely with the verification team. Addressing of Testability aspects of the IP / Subsystem along with functional requirements would be an advantage.
  • Hands on work on pre silicon validation using FPGA/Emulation Board would be a significant added advantage.
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Keyskills :
serialprotocols design ualityconnectivitysolutions

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