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| Job Location | Pune |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Consumer Durables / Electronics |
| Functional Area | Engineering Design / Construction |
| EmploymentType | Full-time |
Skill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verification of PCIe Gen - 2 or Gen - 3. Ethernet 1G / 10G / 40G / 100G and USB 3.0 can also be considered. ,
Keyskills :
open verification methodologymac layerchannel codingchannel estimationinterference cancellationestimationequalizationmultiplexing