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Lead Design Engineer

5.00 to 0.00 Years   Bangalore   26 Oct, 2021
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaGeneral / Other Software,R&D / Product Design
EmploymentTypeFull-time

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Key responsibilities

  • DFT implementation & verification including Scan, PMBIST, JTAG and other DFT s related logic.
  • Working closely with cross functional teams to develop and verify DFT s structures and constraints
  • Work on methodology and Flow development for DFT insertion, pattern development, manufacturing tests, verifications, etc
  • Perform DFT gate level zero delay and timing simulations
  • Participate in ATE bring up, silicon debug and support in system testing
Qualifications
  • 5 years of relevant experience. Degree in Electronics, Electrical or Computer Engineering, graduate level or higher
  • Self-driven, excellent hands-on debug skills and problem solving attitude
  • Clear understanding of key DFT concepts like ATPG, scan compression techniques, fault models (stuck-at, delay tests, IDDQ, Small Delay, etc), IEEE P1500, 1149.1/6, 1687, etc
  • Working knowledge of RTL coding in Verilog, Synthesis & STA
  • Experience in atleast one scripting language like PERL, Python, TCL or Shell is preferred
  • Working knowledge of EDA Functional simulators - Incisive/VCS.
  • Proven success in development of complex custom ASIC products in advanced process nodes
Hands-on experienced and successful taped out several ASICsWe re doing work that matters. Help us solve what others can t.,

Keyskills :
catia v5autocaddrawingweldingbomcontinuous improvement facilitationrtl codinggraduate levelproblem solvingpattern developmentedadftrtlperlatpgjtagtclasic

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