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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Telecom / ISP |
| Functional Area | Embedded, VLSI,Embedded / System Software |
| EmploymentType | Full-time |
What you do at AMD changes everythingAt AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies building blocks for gaming, immersive platforms, and the data center.Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.Physical Design EngineerThe Role:In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Servers and Personal Computers as well as Graphics Cards and VR sets. The DXIO FEINT/Implementation team is responsible for Synthesis, place & Route, Timing closure/CDC/LINT/DFx for very high speed (>2G) design with complex I/O clocking.The Person:As a Senior Design Engineer, you will be working with a diverse team of physical design engineers, RTL design engineers, and managers from NBIO IP team. You will drive physical implementation of IP through the entire physical design flow to achieve best PPA, while shortening the overall development schedule. This role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team!Responsibilities:We are currently looking for a Senior Design Engineer will focus on all physical implementation aspects of next generation IPs. This team deals with multiple I/O protocols including PCIe, SATA, Ethernet & Infinity Fabric link-layer.This team is a group of highly experienced ASIC design engineers working on High speed (>2G) designs with very complex clocking infrastructures. The team owns implementation activities including Synthesis & DFT, floorplan, placement, clock tree synthesis, routing, STA closure. The team will work on cutting edge IP for these I/O protocols to achieve physical implementation with best PPA, including developing reference floorplans, implementation scripts for SoCs worldwide, and support SoCs worldwide. Preferred Experience:3 years or more industry experience in Synthesis, Floor-planning, Placement, clock trees synthesis, Post Route Timing closure for high-speed >=2GHz designs.CDC, PTPX, STA, LINT & DFT, IP, Physical design flow & scripting in TCL, Python Location: Bangalore India Academic Credentials:Minimum B.E. or M.E in Electrical or Computer Engineering (or equivalent)AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability, or any other characteristic protected by law. EOE/MFDVRequisition Number: 116144 Country/Region/Location: India State/Province: Karnataka City: Bangalore Job Function: DesignApply nowApply nowApply for JobEnter your email to apply,
Keyskills :
drawingclock tree synthesistechnical compliancechanging the worldtiming closuredftdraftingmodelingrtlcadautocadasic designphysical designdesign flowrtl designplace routetcl