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Job Location | Bangalore |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | Consumer Durables / Electronics |
Functional Area | General / Other Software |
EmploymentType | Full-time |
Analog Layout DesignQualification: BE / ME / B. Tech / M. Tech in EEE/ ECE/ EI/ CSExperience: 4 to 8 yearsNo of Position:Location: BangaloreRequirements:Minimum 3+ years of Design Knowledge in CMOS lower process nodes such as 7nm/ 14nm/ 28nm. Should have worked on Basic Building Blocks Circuit Design of Analog such as Bandgap Reference. Current Mirrors, Sample/ Hold, Comparator, Differential Amplifier, Opamp, Bias Generator, POR/ BOR. High Speed Latch, High Speed Rx Front End. Must understand Fabrication steps, short channel effects, EM, IR Drop, RV Violations. Must understand Matching Device Concepts, ESDS, Latup, Antenna effect, Common Centroid, Interdigitized Matching Tradeoffs. Good to have:Must have worked on atleast one of the Layout Block with Full Ownership. SerDes standards for one of the PCIe. X, SATA, CPRI, Fibre Transceiver. High Speed DLL, PLL, CDR, ADC, DAC, USB1. 1/ USB2. 0, OTG. Power Management Layout Blocks such as LDO, Buck Boost, Switching Regulator for more than 1A regulated Output Current.,
Keyskills :
analog layoutcircuit designpower managementdacadccdrdllldosatacmosbasicfibreboostopampstepsdesignserdesoutput