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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Consumer Durables / Electronics |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
MSEE minimum 5 years of relevant experience doing digital standard cell based IC design using Verilog, synthesis tools, timing analysis and physical verification tools. Experience with mixed signal systems is a mustDesign for testability, scan insertion, scan vector generationFamiliarity with Cadence and Synopsys design toolsDebugging ICs and associated evaluation systems in a lab environmentExperience architecting and implementing DSP functions such as filters and modulators is a plusExperience architecting complex devices in deep submicron technologies is a plusExperience with UVM and System Verilog is a plusPersonal skills : Excellent communication and interpersonal skillsStrong and effective presentation skills, able to operate at multiple levels including senior managementSelf motivatedTake ownership of problemsCreative problem solvingTeam player,
Keyskills :
logic validation verification verilog fpga icdesign mixedsignal standardcell systemverilog scaninsertion timinganalysis personalskills presentationskills physicalverification dsp uvm cell scan ertms esig