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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Consumer Durables / Electronics |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Architect and develop verification environment and testbench components such as BFMs and checkers. Develop comprehensive test plan and implement test cases. Verify design in unit level environment using directed and constrained random testing, assertion- based verification, formal analysis, and functional verification. Write functional cover groups and cover points for coverage closure. Perform RTL code coverage, assertion coverage, functional coverage and gate level simulations. Drive and adopt4 years, equivalent experience in ASIC design and verification. Highly motivated and be able to work both independently and as a member of team. Experience in verifying designs at system level and block level using constrained random verification. Expert in System Verilog and OVM/ UVM based verification. Strong experience in ASIC design verification flows and DV methodologies. Expert in coding SV Testbench, drivers, monitors, scoreboards, checkers Strong and independent design debugging capability. Strong programming and scripting language capability. Expert in using verification tools like VCS, modelsim, Debussy etc Familiar with System Verilog Assertions, Code and Functional Coverage and Formal verification techniques.,
Keyskills :
verificationcustomerrelationsabstractionagreementsbasicasicdesigncodecoveragesystemverilogdesignverificationrtluvmvcsasicdesigntestingverilogdebussymalverification