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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Recruitment Services |
| Functional Area | General / Other SoftwareEngineering Design / Construction |
| EmploymentType | Full-time |
Develop DFT specifications and driving DFT architecture and methods for designsPerform ATPG pattern generation along with custom patterns for IPQualificationsMust have a deep understanding of a DFT related tasks. Including but not limited to scan insertion, memory BIST, Logic BIST, Serdes and IO test, JTAG, and boundary scan logic features on the chipsDeep knowledge of ATE and Functional tests requiredKnowledge of SRAM, CAM and register file internal circuitry and organizationStrong knowledge of logic design techniquesRTL/ Logic design experience is a plusVerification experience is a plusTiming closure and timing constraints for DFT modes is requiredStrong communication and interpersonal skillsExperience with Perl or other scripting languages is requiredDocument the test- benches to make them more usable by other members of the team.Support end operations team on silicon bring- up and yield improvement including pattern generation and debug, failure analysis, ATPG diagnostic flow automation.,
Keyskills :
physicaldesign failureanalysis cam dft perl atpg jtag bist sram scan design serdes rontend logicbist logicdesign boundaryscan timingclosure scaninsertion tests yield