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| Job Location | Bangalore |
| Education | Not Mentioned |
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| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Job ID: JR0190323Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireDFT engineerJob DescriptionRole and Responsibilities DFT domain expertise on ATPG SCAN responsible for coverage improvement at_speed and stuck_at Domain involves Analog IP as well as Test Chip SoC environment includes timing aware GLS closure and delivery of patterns to High Volume ATE team Familiar with Mentor or Tetramax atpg tool is must for this role Technically well verse with SCAN Architecture, implementation in netlist (SCAN Insertion flows) Work with internal teams like Arch/ Design/ STA convergence team to address issues on implementation/ SDC/SDF files Work with Post Silicon team to enable atpg pattern delivery as well as debug Plus for the job but not a must have - ICL/PDL based flow validation Other extended DFT domain knowledge on MBIST BISR/BIRA/JTAG implementation/usage is an advantage Group Profile: Ip Department within Intel India is owns on next gen Analog IPs and Test chips on various process nodes within Intel process and foundry process. Group mission is to make IP production ready to our SOC customers within Intel. Opportunities are available in DFT domain to own complete end to end solution while enabling scan atpg Arch, implementation of logic design on ultiscan controller, coverage improvement and enabling post silicon ATE team with patterns. Looking for DFT ATPG scan centric skillsetQualificationsQualification and Experience Level: MS/MTech and 7 to 10years of experience in Scan ATPG simulation/Debug and collateral deliveryInside this Business GroupIP Engineering Groups (IPG) vision Build IPs that power Intels leadership products and power our customers silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intels silicon design process. IPGs guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0190323BangaloreIP Engineering Group (IPG),
Keyskills :
atpgdftscancoresiliconlogic designbehavioral trainingsocstaglscolordesigntimingfoundryclosurepatternbusinessipsintel