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Job Location | Bangalore |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | Media / Dotcom / Entertainment |
Functional Area | Embedded / System SoftwareEmbedded, VLSI |
EmploymentType | Full-time |
DFT Engineers / Sr. Engineer / MTS / SMTS Specify the DFT Architecture including JTAG functionality, boundary scan, Hierarchical scan, at- speed testing, I/ O testing requirements, MBIST and Repair, Implement Test Logic. Generate and debug test patterns Exposure to EDA tools viz. DC, LogicVision, Fastscan, Tetramax Good knowledge about all DFT concepts & ATPG Flow. Vector Generation, ATPG Pattern Generation, Validation, Scan insertion and validation, Timing Analysis Chip- level DFT insertion with sound knowledge of scan compression, MBIST & JTAG techniques Should have good post silicon DFT bringup and debug experience Hands on in multi- vendor DFT tools Create test plan for complex ASICs and drive the DFT implementation & verification Ability to guide people, multiplex many issues and set priorities Good communication and leadership skills Qualification: B.Tech / M.Tech or equivalent from a reputed University. Experience: 2 - 8 years of relevant experience. Location: Bangalore / Hyderabad APPLY NOW,
Keyskills :
sound pattern mts dft atpg scan eda testing jtag vendor eadershipskills boundaryscan edatools timinganalysis scaninsertion