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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Consumer Durables / Electronics |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
ESSENTIAL FUNCTIONSDevelopment of test benches and tests for module level testing.Development of tests for top level using System Verilog and UVM methodologies.Putting together test plans for module and top level.Running code and functional coverage.Run Gate level simulations at module and top level.REQUIREMENTSExperience in the range of 1-3 years.Experience with mixed signal designs is a plus understanding of modelling of Analog functions and digital mixed signal in C, Python, Matlab is a plus.,
Keyskills :
verification uvm design failureanalysis ip mixedsignal systemverilog ertms tests python matlab verilog running BiCMOS PowerManagement SerDes CMOS VCO haseLockedLoop