Inviting applicants for IP Logic design engineer

Job Description

Job ID: JRhidden_mobileJob Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireIP Logic design engineer Job Description Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLT is part of the Chipsets Silicon Group, CSG within Design Engineering Group, DEG and is responsible for developing soft IPs, subsystems and gaskets for client and server chipsets. Candidate will be responsible for pre-silicon validation and verification, work closely with the Architect, Micro-architecture and Design teams in determining the proper validation strategy for new design, defining and feedback on verification plans, develop and implement White Box Coverage plans, participate and review validation codes for efficiency and coverage, and drive any paradigm shifts needed in Validation execution. Responsibilities including but not limited to: - Defining and implementing the validation testplan, - Validating and verifying the functionality of new architectural features of next generation designs by developing testplan, tests content or test tools. - Finding and implementing corrective measures for failing RTL tests - Developing automated tools or scripts for the pre-silicon validation environment. - Technically leading a team of validation engineers to achieve validation goals. Excellent communication and organization skills are critical, along with teamwork, and must demonstrate strong technical leadership skills, passion for pre-silicon validation and verification tools and methodology and strong influencing skills. Candidate must have strong orientation for Quality, Commit and Deliver, drive Innovation and efficiencies, and have strong strategic thinking to come up with paradigm shift solutions to critical design and validation challenges.Qualifications The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate must have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Other technical requirements: - 7+ years of relevant pre silicon verification experience with multiple project cycles. - 3 +years of experience in SIP and HIP interoperability verification. - Capable in developing test plan and contents and coverage points for validation purpose based on High Level Architecture specifications. - experienced in Power-aware design and validation flows. - Strong analysis debugging skills and creative in problem solving. - experienced with various tools and methodologies including but not limited to: o System Verilog for design and verification, o Python, Perl, Shell scripting, o logic simulators and debuggers from major EDAs, o RTL model build and testbench development flow, o coverage based random constraint simulation. Candidate will have advantage if experienced in any below: - experienced in UFS, SATA, AMBA, PCI express or any industry standard BUS protocol. - strong chipset CPU level understanding required on power consumption, power estimation and low power verification methods. - design for test, design for verification.Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore s Law and groundbreaking innovations. DEG is Intel s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJRhidden_mobileBangaloreDesign Engineering Group,

Keyskills :
controllingdiagnosticsfftgsmhigh level architecturecontinuous improvement facilitationwhite boxlogic designsystem verilog