IP Design Verification Engineer

Job Description

Job ID: JR0180604Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireIP Design Verification EngineerJob DescriptionDevelops pre Silicon functional validation tests to verify system will meet design requirements. Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing. The candidate will work as a member of a verification team, playing a key/leading role in developing Ethernet Network Interface Controller products. The responsibilities will include but not be limited to below Create, review and signoff verification test plans. Drive/Participate in discussions across various disciplines to get a clear understanding of product features and its validation requirements. Develop the architecture and design of the verification environment in OVM/UVM Development of test-plans, test-bench, BFMs, checkers, monitors/trackers, scoreboard and functional coverage Develop/run/debug tests in System Verilog. Mentor other engineers in using the verification infrastructure and creating test benches. Ownership of verification of block/cluster/ip/subsystem or chip level testing. Drive and participate in verification code, func coverage, RTL code coverage reviews and provide/implement feedback across the project Contribute to the development and maintenance of long term design verification strategy. Track progress of self/sub team to achieve goals timely. Provide indicators and guidance to management on issues and roadblocks on a timely basis. Be able to work with teams across geos. Should be able to contribute as IC or technically leading a group of team for a Focus/CTE as per requirementQualificationsB.E/B.Tech or M.E/M.Tech + 7-9 years of domain experience out of which at least 5 years of hands-on verification experience using SV and OVM/UVMProficiency in SV, OVM, UVM and object oriented programming Strong understanding of engineering design principlesProven track record in ASIC verification from environment development to tests development to validation closureExcellent written and verbal communication skills Very good at creation of test plans, schedules and cost estimates for design verification effortsExperience in development and deployment of verification strategies and methodologies across teams and organizationsApart from simulation, should have work experience with at least one other verification aspect like Performance modeling, Formal verification, Gate Level verification, Emulation, etc. Very good knowledge of a vertical networking or connectivity technology or protocol. E.g. PCIE, Ethernet, Packet Processing, RDMA, Memory Controller, etcProficiency in scripting languages and utilities including Make, Perl, Python, etc.Expert level knowledge of simulation tools such as VCS from SynopsysVery good knowledge of automation concepts and significant experience working with SCM/CI tools and infrastructureExperience in network ASIC design verification is a plus with protocols such as Ethernet, Memory buses, PCI-Express, AMBA protocols, RDMA, etcHands on Experience in C/C++ is highly desirableInside this Business GroupThe Data Center Group (DCG) is at the heart of Intel s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies spanning software, processors, storage, I/O, and networking solutions that fuel cloud, communications, enterprise, and government data centers around the world.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0180604BangaloreData Center Group,

Keyskills :
uvmdata centerverificationobject oriented programmingcode coveragedesignasic designasic verificationcommercial modelsfailure analysissystem simulation